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rev. 4702h?rke?09/04 features pll transmitter ic with single-ended output high output power (6 dbm) at 8.1 ma (315 mhz) and 8.5 ma (433 mhz) typical values divide by 24 ( ATA5756) and 32 ( ata5757 ) blocks for 13 mhz crystal frequencies and for low xto start-up times modulation scheme ask/fsk with internal fsk switch up to 20 kbaud manchester coding, up to 40 kbaud nrz coding power-down idle and power-up modes to adjust corresponding current consumption through ask/fsk/enable input pins enable input for parallel usage of controlling pins in a 3-wire bus system clk output switches on if the crystal current amplitude has reached 35% to 80% of its final value crystal oscillator time until clk output is activated, typically 0.6 ms supply voltage 2.0 v to 3.6 v in operation temperature range of -40 c to 125 c esd protection at all pins (4 kv hbm) small package msop10 benefits low parasitic fsk switch integrated very short and reproducible time to transmit typically < 0.85 ms 13.125 mhz/13.56 mhz crystals give opportunity for small package sizes description the ATA5756/ata5757 is a pll transmitter ic which has been developed for the demands of rf low-cost transmission systems at data rates up to 20 kbaud manches- ter coding and 40 kbaud nrz coding. the transmitting frequency range is 313 mhz to 317 mhz (ATA5756) and 432 mhz to 448 mhz (ata5757), respectively. it can be used in both fsk and ask systems. due to its shorten crystal oscillator settling time it is well suited for tire pressure monitoring (tpm) and for passive entry go applications. figure 1. system block diagram demod. if amp lna vco pll xto control u3741b/ u3745b/ t5743/ t5744/ 1...3 c power amp. xto vco pll ATA5756/ ata5757 antenna antenna uhf ask/fsk tpm and remote control transmitter uhf ask/fsk remote control receiver encoder atarx9x 1 li cell keys uhf ask/fsk transmitter ATA5756 ata5757
2 ATA5756/ata5757 4702h?rke?09/04 pin configuration figure 2. pinning msop10 1 2 3 4 10 9 8 7 clk ask fsk ant2 enable gnd vs xto1 ATA5756 ata5757 5 ant1 6 xto2 pin description pin symbol function configuration 1clk clock output signal for the microcontroller. the clock output frequency is set by the crystal to f xtal /8. the clk output stays low in power- down mode and after enabling of the pll. the clk output switches on if the oscillation amplitude of the crystal has reached a certain level. 2ask switches on the power amplifier for ask modulation and enables the pll and xto if the enable pin is open 3fsk switches off the fsk switch (switch has high z if signal at pin fsk is high) and enables the pll and the xto if the enable pin is open clk vs 100 100 200k ask 50k v ref = 1.1v 20 a 200k fsk 200k v ref = 1.1v 5 a 200k
3 ATA5756/ata5757 4702h?rke?09/04 4 ant2 emitter of antenna output stage 5 ant1 open collector antenna output 6 xto2 diode switch, used for fsk modulation 7 xto1 connection for crystal 8 vs supply voltage see esd protection circuitry (see figure 12) 9 gnd ground see esd protection circuitry (see figure 12) 10 enable enable input if enable is connected to gnd and the ask or fsk pin is high, the device stays in idle mode. in normal operation enable is left open and ask or fsk is used to enable the device. pin description pin symbol function configuration ant1 ant2 xto2 210 a (fsk < 0.25v) and (enable > 1.7v) xto1 1.2k vs 1.5k vs 182 a enable 150k 30 a (fsk >1.7 v ) or (ask > 1.7 v) 250k vs
4 ATA5756/ata5757 4702h?rke?09/04 figure 3. block diagram general description this fully integrated pll transmitter allows the design of simple, low-cost rf miniature transmitters for tpm and rke applications. the vco is locked to 24 f xtal /32 f xtal for ATA5756/ata5757. thus, a 13.125 mhz/13.56 mhz crystal is needed for a 315 mhz/433.92 mhz transmitter. all other pll and vco peripheral elements are integrated. the xto is a series resonance (current mode) oscillator. only one capacitor and a crystal connected in series to gnd are needed as external elements in an ask system. the internal fsk switch, together with a second capacitor, can be used for fsk modulation. the crystal oscillator needs typically 0.6 ms until the clk output is activated if a crystal as defined in the electrical characteristics is used (e.g., tpm crystal). for most crystals used in rke systems, a shorter time will result. the clk output is switched on if the amplitude of the current flowing through the crystal has reached 35% to 80% of its final value. this is synchronized with the 1.64/1.69 mhz clk output. as a result, the first period of the clk output is always a full period. the pll is then locked <250 s after clk output ac tivation. this means an additional wait time of 250 s is necessary before the pa can be switched on and the data transmis- sion can start. this results in a significantly lower time of about 0.85 ms between enabling the ATA5756/ata5757 and the beginning of the data transmission which saves battery power especially in tire pressure monitoring systems. clk fsk ant2 ant1 enable gnd vs xto2 1 3 4 5 6 8 9 10 vco lf cp f 24/ xto pll pa f 8 power up/down ATA5756 / ata5757 pfd ask 2 xto1 7 en or en ampl. ok 32
5 ATA5756/ata5757 4702h?rke?09/04 the power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance and can therefore be controlled via the connected load impedance. this output configuration enables a simple matching to any kind of antenna or to 50 ? . a high power efficiency for the power amplifier results if an optimized load impedance of z load, opt = 380 ? + j340 ? (ATA5756) at 315 mhz and z load, opt = 280 ? + j310 ? (ata5757) at 433.92 mhz is used at the 3-v supply voltage. functional description if ask = low, fsk = low and enable = open or low, the circuit is in power-down mode consuming only a very small amount of current so that a lithium cell used as power supply can work for many years. if the enable pin is left open, enable is the logical or operation of the ask and fsk input pins. this means, the ic can be switched on by either the fsk of the ask input. if the enable pin is low and ask or fsk are high, the ic is in idle mode where the pll, xto and power amplifier are off and the microcontroller ports controlling the ask and fsk inputs can be used to control other devices. this can help to save ports on the microcontroller in systems where other devices with 3-wire interface are used. with fsk = high and ask = low and enable = open or high, the pll and the xto are switched on and the power amplifier is off. when the amplitude of the current through the crystal has reached 35% to 80% of its final amplitude, the clk driver is automatically activated. the clk output st ays low until the clk driver has been acti- vated. the driver is activated synchronously with the clk output frequency, hence, the first pulse on the clk output is a complete period. the pll is then locked within <250 s after the clk driver has been activated, and the transmitter is then ready for data transmission. with ask = high the power amplifier is switched on. this is used to perform the ask modulation. during ask modulation the ic is enabled with the fsk or the enable pin. with fsk = low the switch at pin xto2 is closed, with fsk = high the switch is open. to achieve a faster start-up of the crystal oscillator, the fsk pin should be high during start-up of the xto because the series resistance of the resonator seen from pin xto1 is lower if the switch is off. the different modes of the ATA5756/ata5757 are listed in table 1, the corresponding current consumption values can be found in the table ?electrical characteristics? on page 15. table 1. ATA5756/ata5757 modes ask pin fsk pin enable pin mode low low low/open power-down mode, fsk switch high z low low high power-up, pa off, fsk switch low z low high high/open power-up, pa off, fsk switch high z high low high/open power-up, pa on, fsk switch low z high high high/open power-up, pa on, fsk switch high z low/high high low idle mode, fsk switch high z high low/high low idle mode, fsk switch high z
6 ATA5756/ata5757 4702h?rke?09/04 transmission with enable = open ask mode the ATA5756/ata5757 is activated by enable = open, fsk = high, ask = low. the microcontroller is then switched to external clocking. after typically 0.6 ms, the clk driver is activated automatically (i.e., the microcontroller waits until the xto and clk are ready). after another time period of 250 s, the pll is locked and ready to transmit. the output power can then be modulated by means of pin ask. after transmission, ask is switched to low and the microcontroller returns back to internal clocking. then, the ATA5756/ata5757 is switched to power-down mode with fsk = low. figure 4. timing ask mode with enable not connected to the microcontroller fsk mode the ATA5756/ata5757 is activated by fsk = high, ask = low. the microcontroller is then switched to external clocking. after typi cally 0.6 ms, the clk driver is activated automatically (i.e., the microcontroller waits until the xto and clk are ready. after another time period of 250 s, the pll is locked and ready to transmit. the power amplifier is switched on with ask = h. the ATA5756/ata5757 is then ready for fsk modulation. the microcontroller starts to switch on and off the capacitor between the crystal load capacitor and gnd by means of pin fsk, thus, changing the reference fre- quency of the pll. if fsk = l the output frequency is lower, if fsk = h output frequency is higher. after transmission, fsk stays high and ask is switched to low and the microcontroller returns back to internal clocking. then, the ATA5756/ata5757 is switched to power-down mode with fsk = low. figure 5. timing fsk mode with enable not connected to the microcontroller fsk clk power-up, pa off ask ? t xto power-down power-up, pa on (high) > 250 s power-down power-up, pa off (low) fsk clk power-up, pa off ask ? t xto power-down power-up, pa on (f rf = high) > 250 s power-down power-up, pa off (f rf = low)
7 ATA5756/ata5757 4702h?rke?09/04 transmission with enable = high fsk mode the ATA5756/ata5757 is activated by enable = high, fsk = high and ask = low. the microcontroller is then switched to external clocking. after typically 0.6 ms, the clk driver is activated automatically (i.e., the microcontroller waits until the xto and clk are ready). after another time period of 250 s, the pll is locked and ready to transmit. the power amplifier is switched on with ask = h. the ATA5756/ata5757 is then ready for fsk modulation. the microcontroller starts to switch on and off the capacitor between the crystal load capacitor and gnd by means of pin fsk, thus, changing the reference frequency of the pll. if fsk = l the output frequency is lower, if fsk = h output frequency is higher. after transmission, ask is switched to low and the micro- controller returns back to internal clocking. then, the ATA5756/ata5757 is switched to power-down mode with enable = low and fsk = low. figure 6. timing fsk mode with enable connected to the microcontroller ask mode the ATA5756/ata5757 is activated by enable = high, fsk = high and ask = low. after activation the microcontroller is switch ed to external clocking. after typically 0.6 ms, the clk driver is activated automatically (the microcontroller waits until the xto and clk are ready). after another time period of 250 s, the pll is locked and ready to transmit. the output power can then be modulated by means of pin ask. after transmis- sion, ask is switched to low and the microcon troller returns back to internal clocking. then, the ATA5756/ata5757 is switched to power-down mode with enable = low and fsk = low. fsk clk power-up, pa off ask ? t xto power-down power-up, pa on (f rf = high) > 250 s power-down power-up, pa off (f rf = low) enable
8 ATA5756/ata5757 4702h?rke?09/04 figure 7. timing ask mode with enable connected to the microcontroller accuracy of frequency deviation the accuracy of the frequency deviation using the xtal pulling method is about 20% if the following tolerances are considered. one important aspect is that the values of c 0 and c m of typical crystals are strongly correlated which reduces the tolerance of the fre- quency deviation. figure 8. tolerances of frequency modulation using a crystal with a motional capacitance of c m = 4.37 ff 15%, a nominal load capacitance of c lnom = 18 pf and a parallel capacitance of c 0 = 1.30 pf correlated with c m results in c 0 = 297 c m ( the correlation has a tolerance of 10%, so c 0 = 267 to 326 c m ). if using the internal fsk switch with c switch = 0.9 pf 20% and estimated parasites of c stray = 0.7 pf 10%, the resulting c 4 and c 5 values are c 4 = 10 pf 1% and c 5 = 15 pf 1% for a nominal frequency deviation of 19.3 khz with worst case tol- erances of 15.8 khz to 23.2 khz. fsk clk power-up, pa off ask ? t xto power-down power-up, pa on (high) > 250 s power-down power-up, pa off (low) enable ~ ~ v s xtal c m l m r s c 0 c stray c 4 c 5 crystal equivalent circuit c switch
9 ATA5756/ata5757 4702h?rke?09/04 accuracy of the center frequency the imaginary part of the impedance in large signal steady state oscillation im xto , seen into the pin 7 (xto1), causes some additional frequency tolerances, due to pulling of the xto oscillation frequency. these tolerances have to be added to the tolerances of the crystal itself (adjustment tolerance, temperature stability and ageing) and the influ- ence to the center frequency due to tolerances of c 4 , c 5 , c switch and c stray . the nominal value of im xto = 110 ? , c switch and c stray should be absorbed into the c 4 and c 5 values by using a crystal with known frequency and choosing c 4 and c 5 , so that the xto cen- ter frequency equals the crystal frequency, and the frequency deviation is as expected. then, from the nominal value, the im xto has 90 ? tolerances, using the pulling formula p = -im xto c m f xto with f xto = 13.56 mhz and c m = 4.4 ff an additional fre- quency tolerance of p = 16.86 ppm results. if using crystals with other c m the additional frequency tolerance can be calculated in the same way. for example, a lower c m = 3.1 ff will reduce the frequency tolerance to 11.87 ppm, where a higher c m = 5.5 ff increases the tolerance to 21.07 ppm. clk output an output clk signal of 1.64 mhz (ATA5756 operating at 315 mhz) and 1.69 mhz (ata5757 operating at 433.92 mhz) is provided for a connected microcontroller. the delivered signal is cmos-compatible with a high and low time of >125 ns if the load capacitance is lower than 20 pf. the clk output is low in power-down mode due to an internal pull-down resistor. after enabling the pll and xto the signal stays low until the amplitude of the crystal oscillator has reached 35% to 80% of its amplitude. then, the clk output is activated synchronously with its output signal so that the first period of the clk output signal is a full period. clock pulse take-over by microcontroller the clock of the crystal oscillator can be used for clocking the microcontroller. atmel?s atarx9x microcontroller family provides the special feature of starting with an inte- grated rc oscillator to switch on the ATA5756/ata5757?s external clocking and to wait automatically until the clk output of the ATA5756/ata5757 is activated. after a time period of 250 s the message can be sent with crystal accuracy. output matching and power setting the output power is set by the load impedance of the antenna. the maximum output power is achieved with a load impedance of z load, opt = 380 ? + j340 ? (ATA5756) at 315 mhz and z load, opt = 280 ? + j310 ? (ata5757) at 433.92 mhz. a low resistive path to v s is required to deliver the dc current (see figure 9 on page 10). the power amplifier delivers a current pulse and the maximum output power is delivered to a resistive load if the 0.66 pf output capacitance of the power amplifier is compen- sated by the load impedance. at the ant1 pin, the rf output amplitude is about v s - 0.5 v. the load impedance is defined as the impedance seen from the ATA5756?s ant1, ant2 into the matching network. do not mix up this large-signal load impedance with a small-signal input impedance delivered as an input characteristic of rf amplifiers. the latter is measured from the application into the ic instead of from the ic into the application for a power amplifier. the 0.66 pf output capacitance absorbed into the load impedance a real impedance of 684 ? (ATA5756) at 315 mhz and 623 ? (ata5757) at 433.92 mhz should be mea- sured with a network analyses at pin 5 (ant1) with the ATA5756/ata5757 soldered, an optimized antenna connected and the power amplifier switched off. less output power is achieved by lowering the real parallel part where the parallel imag- inary part should be kept constant. lowering the real part of the load impedance also reduces the supply voltage dependency of the output power.
10 ATA5756/ata5757 4702h?rke?09/04 output power measurement can be done with th e circuit as shown in figure 9. please note that the component values must be changed to compensate the individual board parasitics until the ATA5756/ata5757 has the right load impedance. also, the damping of the cable used to measure the output power must be calibrated. figure 9. output power measurement ATA5756/ata5757 table 2 and table 3 show the output power and the supply current versus temperature and supply voltage. table 2. output power and supply current versus temperature and supply voltage for the ATA5756 with z load = 380 ? + j340 ? (correlation tested) ambient temperature v s = 2.0 v (dbm/ma) v s = 3.0 v (dbm/ma) v s = 3.6 v (dbm/ma) t amb = -40c 3.1 1.5 / 7.2 6.1 +2/-3 / 7.7 7.1 +2/-3 / 7.9 t amb = +25c 3.0 1.5 / 7.5 6.0 2 / 8.1 7.4 2 / 8.3 t amb = +85c 3.0 1.5 / 7.5 5.8 +2/-3 / 8.2 7.2 +2/-3 / 8.5 t amb = +125c 2.5 1.5 / 7.6 5.5 +2/-3 / 8.2 6.5 +2/-3 / 8.5 table 3. output power and supply current versus temperature and supply voltage for the ata5757 with z load = 280 ? + j310 ? (correlation tested) ambient temperature v s = 2.0 v (dbm/ma) v s = 3.0 v (dbm/ma) v s = 3.6 v (dbm/ma) t amb = -40c 3.3 1.5 / 7.6 6.2 +2/-3 / 8.1 7.1 +2/-3 / 8.4 t amb = +25c 3.0 1.5 / 8.0 6.0 2 / 8.5 7.5 2 / 8.8 t amb = +85c 2.8 1.5 / 8.0 5.7 +2/-3 / 8.6 6.8 +2/-3 / 8.8 t amb = +125c 2.7 1.5 / 8.1 5.5 +2/-3 / 8.7 6.6 +2/-3 / 8.9 ~ ~ ant2 ant1 r in power meter c 1 = 1n l 1 = 68 nh/ 39 nh c 2 = 2.2 pf/1.8 pf z lopt v s z = 50 ? 50 ?
11 ATA5756/ata5757 4702h?rke?09/04 application circuits for the supply voltage blocking capacitor c 3 , a value of 68 nf/x7r is recommended (see figure 10 on page 12 and figure 11 on page 13). c 1 and c 2 are used to match the loop antenna to the power amplifier. for c 2 , two capacitors in series should be used to achieve a better tolerance value and to enable it to realize z load,opt by using capacitors with standard values. together with the pins of ATA5756 and the pcb board wires, c 1 forms a series resonance loop that suppresses the 1 st harmonic, hence the position of c 1 on the pcb is important. normally, the best suppression is achieved when c 1 is placed as close as possible to the pins ant1 and ant2. the loop antenna should not exceed a width of 1.5 mm, otherwise the q-factor of the loop antenna is too high. l 1 (50 nh to 100 nh) can be printed on the pcb. c 4 should be selected so that the xto runs on the load resonance frequency of the crystal. normally, a value of 10 pf results in a 12 pf load-capacitance crystal due to the board parasitic capacitances and the inductive impedance of the xto1 pin.
12 ATA5756/ata5757 4702h?rke?09/04 figure 10. ask application circuit ant2 ant1 enable atarx9x c3 vs c1 vs c4 loop antenna bpxy osc1 7 bpxy bpxy vss 20 vdd 1 vs l1 xtal c2 s1 s2 bpxy clk fsk gnd vs xto2 1 3 4 5 6 8 9 10 vco lf cp f 24/ xto pll pa f 8 power up/down ATA5756/ata5757 pfd ask 2 xto1 7 en or en ampl. ok 32
13 ATA5756/ata5757 4702h?rke?09/04 figure 11. fsk application circuit ant2 ant1 enable atarx9x c3 vs c1 vs c4 loop antenna bpxy osc1 7 bpxy bpxy vss 20 vdd 1 vs l1 xtal c2 s1 s2 bpxy clk fsk gnd vs xto2 1 3 4 5 6 8 9 10 vco lf cp f 24/ xto pll pa f 8 power up/down ATA5756/ata5757 pfd ask 2 xto1 7 en or en ampl. ok c5 32
14 ATA5756/ata5757 4702h?rke?09/04 figure 12. esd protection circuit clk fsk ant2 ant1 xto1 enable vs gnd xto2 ask absolute maximum ratings parameters symbol minimum maximum unit supply voltage v s 5v power dissipation p tot 100 mw junction temperature t j 150 c storage temperature t stg -55 125 c ambient temperature t amb1 -55 125 c ambient temperature in power-down mode for 15 minutes without damage with v s 3.2 v v enable < 0.25 v or enable is open, v ask < 0.25 v, v fsk < 0.25 v t amb2 175 c input voltage v maxask -0.3 (v s + 0.3) (1) v note: 1. if v s + 0.3 is higher than 3.7 v, the maximum voltage will be reduced to 3.7 v. thermal resistance parameters symbol value unit junction ambient r thja 170 k/w
15 ATA5756/ata5757 4702h?rke?09/04 electrical characteristics v s = 2.0 v to 3.6 v, t amb = -40c to 125c unless otherwise specified. typical values are given at v s = 3.0 v and t amb = 25c. all parameters are referred to gnd (pin 9). c m = 4.37 ff, c 0 = 1.3 pf, c lnom = 18 pf, c 4 = 10 pf, c 5 = 15 pf and r s 60 ? parameters test conditions symbol min. typ. max. unit supply current, power-down mode v enable < 0.25 v or enable is open, v ask < 0.25 v, v fsk < 0.25 v t amb = 25 c t amb = -40 c to +85 c t amb = -40 c to +125 c i s_off 1 100 350 7,000 na na na supply current, idle mode v enable < 0.25 v, v s 3.2 v ask,fsk can be low or high i s_idle 100 a supply current, power-up, pa off, fsk switch high z v s 3.2 v, v fsk > 1.7 v, v ask < 0.25 v enable is open i s 3.6 4.6 ma supply current, power-up, pa on, fsk switch high z v s 3.2 v, c clk 10 pf v fsk > 1.7 v, v ask > 1.7 v enable is open ATA5756 ata5757 i s_transmit1 8.1 8.5 9.8 10.5 ma ma supply current, power-up, pa on, fsk low z v s 3.2 v, c clk 10 pf v fsk < 0.25 v, v ask > 1.7 v enable is open ATA5756 ata5757 i s_transmit2 8.4 8.8 10.2 11.0 ma ma output power v s = 3.0 v, t amb = 25 c, f = 315 mhz for ata 5 7 5 6 , z load, opt = (380 + j340) ? f = 433.92 mhz for ata5757 , z load, opt = (280 + j310) ? p out 4 6 8 dbm output power for the full temperature and supply voltage range t amb = -40c to +125 c, v s = 2.0 v to 3.2 v p out 1 8.2 dbm spurious emission f clk = f xt0 /8 load capacitance at pin clk 20 pf f 0 f clk f 0 f xt0 other spurious are lower spour -42 -60 dbc harmonics with 50 ? matching network according to figure 9 2nd 3rd -16 -15 dbc dbc oscillator frequency xto (= phase comparator frequency) f xto = f 0 /24 ATA5756 f xto = f 0 /32 ata5757 f xtal = resonant frequency of the xtal, c m = 4.37 ff, load capacitance selected accordingly t amb = -40c to +85c t amb = -40c to +125c ? f xto -14.0 -17.5 f xtal f xtal +14.0 +17.5 ppm ppm
16 ATA5756/ata5757 4702h?rke?09/04 imaginary part of xto1 impedance in steady state oscillation since pulling p is p = -im xto c m f xto ? f xto can be calculated out of im xto with c m = 4.37 ff im xto j20 j110 j200 ? real part of xto1 impedance in small signal oscillation this value is important for crystal oscillator start-up re xto -650 -1100 ? crystal oscillator start-up time time between enable of the ic with fsk = h and activation of the clk output. the clk is activated synchronously to the output frequency if the current through the xtal has reached 35% to 80% of its maximum amplitude. crystal parameters: c m = 4.37 ff, c 0 = 1.3 pf, c lnom = 18 pf, c 4 = 10 pf, c 5 = 15 pf, r s 60 ? ? t xto 0.6 1.4 ms xto drive current current flowing through the crystal in steady state oscillation (peak-to-peak value) i dxto 300 app locking time of the pll time between the activation of clk and when the pll is locked (transmitter ready for data transmission) ? pll 250 s pll loop bandwidth f loop_pll 250 khz in loop phase noise pll 25 khz distance to carrier l pll -85 -76 dbc/hz phase noise vco at 1 mhz at 36 mhz l at1m l at36m -90 -121 -84 -115 dbc/hz dbc/hz frequency range of vco ATA5756 ata5757 f vco 310 432 317 448 mhz mhz clock output frequency (cmos microcontroller compatible) ATA5756 ata5757 f clk f 0 /192 f 0 /256 mhz clock output minimum high and low time c load 20 pf, high = 0.8 vs, low = 0.2 v s , f clk < 1.7 mhz t clklh 125 ns series resonance resistance of the resonator seen from pin xto1 for proper detection of the xto amplitude r s_max 150 ? capacitive load at pin xto1 c l_max 5 pf fsk modulation frequency rate this corresponds to 20 kbaud in manchester coding and 40 kbaud in nrz coding f mod_fsk 0 20 khz fsk switch off resistance high z r swit_off 50 k ? fsk switch off capacitance high z capacitance c swit_off 0.75 0.9 1.1 pf fsk switch on resistance low z r swit_on 130 175 ? ask modulation frequency rate duty cycle of the modulation signal = 50%, this corresponds to 20 kbaud in manchester coding and 40 kbaud in nrz coding f mod_ask 0 20 khz electrical characteristics (continued) v s = 2.0 v to 3.6 v, t amb = -40c to 125c unless otherwise specified. typical values are given at v s = 3.0 v and t amb = 25c. all parameters are referred to gnd (pin 9). c m = 4.37 ff, c 0 = 1.3 pf, c lnom = 18 pf, c 4 = 10 pf, c 5 = 15 pf and r s 60 ? parameters test conditions symbol min. typ. max. unit
17 ATA5756/ata5757 4702h?rke?09/04 ask input low level input voltage high level input voltage input current high v il v ih i in 1.7 0.25 v s 30 v v a fsk input low level input voltage high level input voltage input current high v il v ih i in 1.7 0.25 v s 30 v v a enable input low level input voltage high level input voltage input current high input current low v il v ih i inh i inl 1.7 -40 -40 0.25 v s 40 40 v v a a electrical characteristics (continued) v s = 2.0 v to 3.6 v, t amb = -40c to 125c unless otherwise specified. typical values are given at v s = 3.0 v and t amb = 25c. all parameters are referred to gnd (pin 9). c m = 4.37 ff, c 0 = 1.3 pf, c lnom = 18 pf, c 4 = 10 pf, c 5 = 15 pf and r s 60 ? parameters test conditions symbol min. typ. max. unit
18 ATA5756/ata5757 4702h?rke?09/04 package information msop10 ordering information extended type number package remarks ATA5756-6dq msop10 ? ata5757-6dq msop10 ?
19 ATA5756/ata5757 4702h?rke?09/04 revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. changes from rev. 4702d - 02/04 to rev. 4702e - 07/04 1. abs. max. ratings table (page 14): row ?input voltage? added 2. abs. max. ratings table (page 14): table note 1 added 3. el. char. table (page 17): rows ?ask input?, ?fsk input?, ?enable input? maxi- mum values changed changes from rev. 4702e - 07/04 to rev. 4702f - 08/04 1. preliminary deleted changes from rev. 4702f - 08/04 to rev. 4702g - 08/04 1. electrical characteristics table, page 15, row ?output power variation...?. -> the word ?variation? deleted changes from rev. 4702g - 08/04 to rev. 4702h - 09/04 1. electrical characteristics table, page 15, row ?output power for the full...?. -> maximum value changed
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature 4702h?rke?09/04 ? atmel corporation 2004 . all rights reserved. atmel ? and combinations thereof are the registered tradem arks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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